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Selected
Publications by Cambridge Analog Technologies Staff
Analog-to-Digital Converters - Digitizing the Analog
World, Proceedings of the IEEE, Feb., 2008;
Invited paper by Hae-Seung Lee and Charlie Sodini
Comparator-Based Switched-Capacitor Circuits for
Scaled CMOS Technologies, IEEE Journal of Solid
State Circuits, Dec. 2006, co-authored by Hae-Seung
Lee
A Zero-Crossing-Based 8b 200MSps Pipelined ADC,
Journal of Solid State Circuits, Dec. 2006 by
Lane Brooks and Hae-Seung Lee
Limits of
Power Consumption, Keynote Address by Hae-Seung
Lee, VLSI Symp., Kyoto, June, 2007
A 15b 1 Msps Digitally Self-Calibrated Pipeline ADC,
IEEE Journal of Solid State Circuits, Dec. 1993,
co-authored by Hae-Seung Lee
A Self-Calibrating 15 Bit CMOS AD Converter,
IEEE Journal of Solid State Circuits, Dec. 1984 by
Hae-Seung Lee et al.
Low-Power Reconfigurable Analog-to-Digital
Converters, Invited Keynote by Kush Gulati,
Sixth IEEE Dallas Circuits and Systems Workshop,
November, 2007
Reconfigurable ADCs for
Multi-mode Terminals, Invited Workshop by Kush
Gulati, IEEE RFIC
Symposium, Honolulu, June, 2007
A Highly-Integrated CMOS Analog Baseband Transceiver
with 180MSPS 13b Pipelined CMOS ADC and Dual 12b
DACs," IEEE Journal of Solid-State Circuits,
August 2006 by Kush Gulati, Carlos Munoz et. al.
A Low-Power Reconfigurable Analog-to-Digital
Converter," IEEE Journal of Solid-State
Circuits, December, 2001 by Kush Gulati and
Hae-Seung Lee
A 3.3-V, 500-Mb/s/ch parallel optical receiver in
1.2-um GaAs technology, IEEE Journal of
Solid-State Circuits, December, 1998 by Jungwook
Yang et. al.
A 3M Pixel Low-Noise Flexible Architecture CMOS
Image Sensor, International Solid-State Circuits
Conference, Feb., 2006, by Jungwook Yang, Hae-Seung
Lee et. al.
A 12-Bit, 10-MHz Bandwidth, Continuous-Time
Sigma-Delta ADC With a 5-Bit 950-MSps VCO-Based
Quantizer, IEEE Journal of Solid-State Circuits,
April, 2008 by Matthew Straayer et. al.
A Highly Digital MDLL-Based Clock Multiplier That
Leverages a Self-Scrambling Time-to-Digital
Converter to Achieve Subpicosecond Jitter
Performance, IEEE Journal of Solid-State
Circuits, April, 2008, co-authored by Straayer
A 16mW 8Mbps Fractional-N FSK Modulator at
15.8-18.9GHz, IEEE RFIC Symposium by Matthew
Straayer et. al.
A
Low-Noise, Wide-BW 3.6GHz Digital Delta-Sigma
Fractional-N Frequency Synthesizer with a
Noise-Shaping Time-to-Digital Converter and
Quantization Noise Cancellation, ISSCC 2008,
co-authored by Matthew Straayer
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