Frequently Asked Questions.

How would we simulate the CAT IP within our chip?

An industry-standard encrypted hierarchical spectre netlist that can be instantiated within your schematic is provided to enable such system simulations. Support for other simulation engines is also provided.

What support will CAT provide during the floor-planning and routing of our chip?

The aspect ratio of our IP will be guided by your specifications. To enable place and route and floorplanning of your SoC, whenever, applicable, open access compatible Cadence layout abstract will be available. This abstract view will include connectivity information as well as keep-out regions for metal over-routing.

What support will CAT provide through the bringup of our chip?

We believe our chip will perform robustly within your SoC given the exhaustive simulations and characterization we undertake on the IP. Nevertheless, we take nothing for granted. Our IP will have extensive tuning knobs that can be utilized through the testing process. These knob are accessible through an industry standard interface will be available for your use upon request. We would be happy to assist you through this process. Our team includes world-class circuit designers that have extensive industry backgrounds in building complex SoCs. Consequently, we understand what it takes to make and successfully use an IP such as an ADC in a complex SoC.

How robust is CAT’s proprietary low-power technology?

CAT’s technology is very robust against power supply and substrate noise, and supply variation. We also simulate and test the chip with noise sources that model the noise that you expect on your chip to further ensure the performance of the IP in your SoC. Given that this technology relies less on traditional analog process parameters, it will work better at process corners. CAT rigorously follows recommended manufacturing rules through the design process to ensure superior yield.